The present invention relates to a process for manufacturing a semiconductor integrated circuit device having a ferroelectric (high relative dielectric constant substance) capacitor and, more particularly, to a technique which is effective when applied to a process for manufacturing a ferroelectric (high relative dielectric constant substance) capacitor by using a conductive material for producing reaction products of low vapor pressure at a dry-etching time.
In order to compensate the reduction in the amount of stored charge with the miniaturization of the memory cell of a large capacity DRAM (Dynamic Random Access Memory) exceeding 256 Mbits or 1 Gbits, it is demanded that the capacitor insulating film of a data storing capacitive element (or capacitor) is made of a high relative dielectric material having a specific relative dielectric constant of 20 or more such as Ta.sub.2 O.sub.5 or BST ((Ba, Sr)TiO.sub.3), or a ferroelectric material having a relative dielectric constant over 100 such as PZT (PbZr.sub.x T.sub.1-x O.sub.3), PLT (PbLa.sub.x Ti.sub.1-x O.sub.3), PLZT, PbTiO.sub.3, SrTiO.sub.3 or BaTiO.sub.3.
In the field of a nonvolatile memory, there has been developed a ferroelectric memory which utilizes the polarization inversion of the ferroelectric material for data storage.
When the capacitor insulating film of the capacitor is made of an aforementioned ferroelectric substance (high relative dielectric constant substance), it is necessary to make the conductive films for electrodes sandwiching the capacitor insulating film, of such a refractory metallic material, e.g., Pt having a high affinity with those materials.
When the capacitor is made of Pt or PZT, there arises the following problem. When the thin film of Pt or PZT deposited on the substrate is dry-etched, it is known that a lot of reaction products having a low vapor pressure are deposited on the side face of a pattern to cause the short-circuiting between the capacitors.
In order to prevent reaction products from being deposited on the side face of the pattern when the Pt film is to be dry-etched, there is known in the prior art either a method of tapering the side face of a photoresist used as the etching mask or a method of using a hard mask of a silicon oxide film or a metal film in place of the photoresist.
It has been reported in 27p-N-9, Preprint No. 2 of the 43rd Joint Congress of Applied Physics of Japan 1996, that a clean capacitor without any side wall deposited film can be formed by using a resist mask having a side face tapered at about 75 degrees when a three-layered film of Pt/PZT/Pt deposited on a substrate is dry-etched. This can be thought in the following manner. If the side face of the resist mask is tapered, the side face of the pattern is also irradiated with etching ions so that the etch-off rate is enabled to exceed the deposition rate of the side wall deposited film by increasing the taper angle over a predetermined value (e.g., about 75 degrees).
It has been reported in 26a-ZT-4, Preprint No. 2 of 56th Joint Congress of Applied Physics of Japan 1995, that the Pt film can be tapered to effect the etching without any side wall deposited film, when the Pt film is dry-etched, by using as the mask a silicon oxide film etched to a predetermined pattern and by using an etching gas containing Ar and additional oxygen.
Japanese Patent Laid-Open No. 89662/1993 has disclosed a method of forming an excellent Pt pattern having no side wall deposited film by using as the mask a Ti film etched to a predetermined pattern thereby to etch the Pt film.
The RIE etching technique using a tapered resist mask has been disclosed on pp. 244 to 253, "Glow Discharge Processes SPUTTERING AND PLASMA ETCHING", by Brian Chapman.